1. Field of the Invention
The present invention relates to a polling device for performing communication control, which is applicable to, for example, a host control circuit used in a USB (Universal Serial Bus) system, and a communication apparatus using such a device.
2. Description of the Related Art
In recent years, there has been an increase in opportunity to process audio data, image data, and in particular, successively-moving streaming data, such as motion picture data, using digital equipment. In order to communicate such streaming data, it is necessary to always secure a specific frequency band in a communication path. As communication buses, which enable this, there are USB, IEEE1394, etc. In order to always secure a specific frequency band in a communication path, it is necessary to allow information, which should be communicated, to be allocated within a specific frame period. In a USB transfer method, such information is allocated within a frame period of 1 millisecond (msec) or less.
The mode for securing a specific frequency band in a bus, such as USB, so as to perform an information transfer over the secured frequency band is referred to as an “isochronous transfer”. The transfer methods other than the USB transfer method, e.g., an IEEE1394 transfer method, etc., basically use substantially similar types of transfer modes to those used in the USB transfer method, and therefore descriptions of the variety of types of transfer modes are given only with respect to the case of the USB transfer method.
The USB can connect a host computer and a plurality of devices (up to 127 devices). An address number in the range from 0 to 127 is allocated to each device (address number (device number) 0 is used only immediately after connection), and each device can have up to 16 endpoints (corresponding to communication channels).
Firstly, the host computer divides the time into prescribed time periods referred to as “frames” (each frame corresponds to 1 msec in the case of the USB). The host computer transmits a SOF (Start of Frame) at the beginning of a frame, and then performs an isochronous transfer, as a transfer type, or an interrupt transfer having a length corresponding to n times the length of a frame period, where n is an integer. The isochronous transfer is performed in each frame, while the interrupt transfer is performed for each transfer time interval (hereinafter, referred to as the “interval”). Specifically, the interrupt transfer is performed while counting the number of frames using an interval counter.
Next, after one cycle of the isochronous transfer and/or one cycle of the interrupt transfer are/is performed, the other types of transfers, such as a control transfer of a command and a bulk transfer of data, are performed. The control transfer is preferably performed once per frame, and therefore only the bulk transfer is performed after one cycle of the control transfer is completed. Specifically, after commands are exchanged by the control transfer, units of data are exchanged by the bulk transfer. It should be noted that the isochronous transfer, the interrupt transfer, the control transfer, and the bulk transfer are performed from one of the four types of transfers having the highest priority in transfer.
Referring to FIG. 4, a structural example of a communication system, which realizes the above-described functions, is described.
FIG. 4 is a block diagram illustrating a primary structure of a conventional communication circuit 100. In FIG. 4, the communication circuit 100 includes a 1-millisecond counter (1 ms counter) 101, a controller 102, a polling circuit 103, a transmitter circuit 104, and a receiver circuit 105.
The 1 ms counter 101 counts a prescribed time period of 1 msec, which is a unit of a frame, so as to generate a 1 ms timer signal.
The controller 102 sets the types of transfers, a value of a transfer counter, a value of an interval counter, etc., which are described below with reference to FIG. 5. The interval counter generates a pulse signal for each time period having a length corresponding to n times the length of a prescribed time period of 1 msec, where n is an integer, so as to count the number of frames.
The polling circuit 103 determines the order of priority in transfer, determines whether or not preparations for communication are made, and then outputs a communication request (a transmission request).
The transmitter circuit 104 transmits a data signal to any other equipment 106 according to the transmission request.
The receiver circuit 105 receives a response from the other equipment 106 and sends a transmission completion signal to the polling circuit 103.
FIG. 5 is a block diagram illustrating a detailed structure of the polling circuit 103 shown in FIG. 4. FIG. 6 is a timing chart illustrating the operation of the polling circuit 103. In FIGS. 5 and 6, symbols for the types of transfers “IS”, “IN”, “C”, and “B” denote an isochronous transfer, an interrupt transfer, a control transfer, and a bulk transfer, respectively.
Referring to FIGS. 5 and 6, when a value represented by a 1 ms timer signal output by the 1 ms counter 101 (FIG. 4) becomes “1”, the 1 ms timer signal passes through an OR circuit to a flip flop in an output stage, so that a value represented by a communication request becomes “1”, thereby transmitting a SOF (Start Of Frame). The 1 ms timer signal resets and clears a polling address counter and a polling endpoint counter so as to cause their respective values to become “0”. Further, the 1 ms timer signal resets a state counter so as to cause a value of a state signal to become “00”, and also resets a count-up signal generator circuit so as to cause a value of a count-up signal to become “0”. Furthermore, although not shown in the figures, the interval counter is counted down so as to decrease its value by “1”, and when the value of the interval counter is decreased to “0”, the initial value thereof is loaded into the interval counter.
Next, when the transmission of the SOF is completed, the polling address counter and the polling endpoint counter are reset so as to have the irrespective values “0”, as described above. Similarly, the value represented by the state signal output by the state counter becomes “00”. At this point, the value represented by the count-up signal becomes “1”.
The polling endpoint counter has four endpoint (communication channel) numbers from “0” to “3”. In the case where the count-up signal represents the value “1”, when a clock signal is input to the polling endpoint counter, the polling endpoint counter is counted up so as to increase its value by “1”. As a result, the endpoint number is sequentially changed from “0” through “1” to “2” with inputs of clock signals, and when the endpoint number becomes “3”, a “=3” detection section detects the value “3”. When the next clock signal is input to the polling endpoint counter, the endpoint number returns to “0”.
On the other hand, the polling address counter has three values from “0” to “2”. In the case where the polling endpoint counter has the value “3”, when the next clock signal is input to the polling address counter, the address number is counted up by “1”. When the address number becomes “2”, a “=2” detection section detects the value “2”. When the next clock signal is input to the polling address counter, the address number returns to “0”.
Types of transfers to be performed at endpoints, values of a transfer number counter, and values of an interval counter, which are indicated by the polling address counter and the polling endpoint counter, are read by corresponding registers (not shown) in the polling circuit 103. In the case where the state counter has the value “00”, it is determined whether the isochronous transfer should be performed or whether the interrupt transfer should be performed at the time the interval counter has the value “0”. This determination operation is performed based on the state of an output of a logic circuit which is a determination circuit (including a“=0” detection section, two matching detection circuits, an AND circuit, and an OR circuit). While reading the types of transfers, the values of the transfer number counter and the values of the interval counter, the value represented by the count-up signal is required to be “0”, so as not to count up the polling address counter and the polling endpoint counter.
When the value represented by a state signal output by the state counter is “00”, a value represented by a communication request is caused to be “1” so as to perform a transfer operation. When the communication is completed, a value represented by a communication completion signal becomes “1”, and the value represented by the communication request returns to “0”. When the value represented by the state signal is not “00” or when the communication is completed, the polling address counter and the polling endpoint counter are counted up so as to increase their respective values by “1”. When all of the address numbers and the endpoints are checked, the state counter is counted up so as to cause the value represented by the state signal to become “01”.
When the value represented by the state signal output by the state counter is “01”, the types of transfers to be performed at endpoints, values of the transfer number counter, and values of the interval counter, which are indicated by the polling address counter and the polling endpoint counter, are read by the corresponding registers (not shown) in the polling circuit 103 so as to find a control transfer or a bulk transfer which should be performed at the time the value of the transfer number counter is not “0”. This operation is performed based on the state of an output of a logic circuit which is a determination circuit (including two matching detection circuits, an OR circuit, a “≠0” detection section, and an AND circuit).
When the control transfer or the bulk transfer is found, the value represented by the communication request is caused to be “1” so as to perform a transfer operation. When the communication is completed, the value represented by the communication completion signal becomes “1”, and the value represented by the communication request returns to “0”.
Alternatively, when the control transfer or the bulk transfer is not found or when the communication is completed, the polling address counter and the polling endpoint counter are counted up so as to increase their respective values by “1”. When all of the address numbers and the endpoints are checked, the state counter is counted up so as to cause the value represented by the state signal to become “10”.
Further, when the value represented by the state signal output by the state counter is “10”, the types of transfers to be performed at endpoints, values of the transfer number counter, and values of the interval counter, which are indicated by the polling address counter and the polling endpoint counter, are read by the corresponding registers in the polling circuit 103 so as to find a control transfer which should be performed at the time the value of the transfer number counter is not “0”. This operation is performed based on the state of an output of a logic circuit which is a determination circuit (including two matching detection circuits, an OR circuit, a “≠0” detection section, and an AND circuit).
When the bulk transfer is found, the value represented by the communication request is caused to be “1” so as to perform a transfer operation. When the communication is completed, the value represented by a communication completion signal becomes “1” so as to perform a transfer operation and the value represented by the communication request returns to “0”.
Alternatively, when the bulk transfer is not found or when the communication is completed, the polling address counter and the polling endpoint counter are counted up so as to increase their respective values by “1”. After this, the state signal retains the value “10” (which is the maximum value for the USB). The same operation is repeated until the next 1 ms timer signal is generated.
As described above, when the state signal output by the state counter represents the value “00”, which indicates the highest priority in transfer, an isochronous transfer or an interrupt transfer is performed. Then, transfer operations are processed in the order of priority based on values represented by state signals, such that a transfer operation corresponding to a state signal representing the value “01” is performed first and a transfer operation corresponding to a state signal representing the value “10” is performed last.
In the above-described structure, when the number of devices (to which address numbers are assigned as device numbers) is increased and transfer operations are performed more frequently, the next frame might be started during transmission of a state signal, which represents, for example, the value “01” having the second highest priority in transfer after the value “00” (a signal is compulsorily input for each millisecond in the case of the USB). In the case of a transfer operation corresponding to a state signal having a low priority in transfer, there is the possibility that a transfer operation might never be performed at a specific endpoint (corresponding to a communication channel). Specifically, this could happen in the case where ten devices connected to a communication system substantially simultaneously transmit interrupt transfer requests to the communication system.
A specific example is further provided. As shown in FIG. 6, after the isochronous transfer or the interrupt transfer is performed, the value represented by the state signal becomes “01” and a control transfer or a bulk transfer is started from the endpoint “0” at the address number “0”. When the state where the next frame is started after a transfer operation on the endpoint “2” at the address number “1” is repeatedly created, transfer processing associated with the address number “1”, the endpoint “3”, and all the endpoints at the address number “2” might never be performed.
The USB standard does not permit the occurrence of the case where frequent performances of the isochronous transfer and/or the interrupt transfer cause the next frame to be started during the transmission of a state signal of the state counter, which represents the value “00” having the highest priority in transfer. Examples of such a case include a case where the sound being reproduced is interrupted by the input of a great deal of audio data to a device reproducing the sound. In the case where there is a possibility of such interruption, when a device is connected to a host computer, the host computer may cause the device to be disabled. However, there is a problem that it is unpredictable when the interrupt transfer occurs. Further, there is another problem that a specific frequency band in a communication path is required to be secured.